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STA510F
44-V, 5.5-A, quad power half bridge
Features
! ! ! ! ! ! !
Minimum input output pulse width distortion 150 mW Rdson complementary DMOS output stage CMOS compatible logic inputs Thermal protection thermal warning output Under-voltage protection No power-on, power- off sequence required The device is particularly designed to make the output stage of a stereo all-digital high-efficiency (FFX) amplifier capable of delivering 100 W + 100 W output power into 8- loads with THD = 10% and Vcc = 39 V. In single BTL configuration the device can deliver 200 W into a 4- load with THD = 10% and Vcc = 39 V. The device is fully compatible with the DDX(R) driver device. The input pins have a threshold proportional to VL pin voltage. PowerSO36 with exposed pad (or slug) up
Description
STA510F is a monolithic, quad, half-bridge stage in Multipower BCD technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (binary mode) with half current capability.
Table 1.
Device summary
Operating Temp. range 0 to 70 C Package PowerSO36 (slug up) Tube Packing
Order code STA510F
Figure 1.
Typical application
Output Filter
OUT 1A OUT 1B PWM Out 1A IN 1A IN A OUT A OUT B IN B SPEAKER
PWM Out 2A
IN 2A
STA330
PWM Out 1B IN1B
STA510F Output Filter
PWM Out 2B
IN 2B OUT 2A OUT 2B Vcc IN A OUT A OUT B IN B SPEAKER
Vcc
PSU
GND
December 2007
Rev 1
1/11
www.st.com 11
Pin description
STA510F
1
Pin description
Figure 2. Pin connection (top view)
VCCSign VCCSign VSS VSS IN2B IN2A IN1B IN1A TH_WAR FAULT TRI-STATE PWRDN CONFIG VL VDD VDD GND-Reg GND-Clean
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
D01AU1273
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
GND-SUB OUT2B OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT2A OUT1B OUT1B VCC1B GND1B GND1A VCC1A OUT1A OUT1A N.C.
Table 2.
Pin 1 2, 3 4 5 6 7 8, 9 10, 11 12 13 14 15 16, 17
Pin list
Name GND-SUB OUT2B Vcc2B GND2B GND2A Vcc2A OUT2A OUT1B Vcc1B GND1B GND1A Vcc1A OUT1A Substrate ground Output half bridge 2B Positive Supply Negative Supply Negative Supply Positive Supply Output half bridge 2A Output half bridge 1B Positive Supply Negative Supply Negative Supply Positive Supply Output half bridge 1A Description
2/11
STA510F Table 2.
Pin 18 19 20 21, 22 23 24 25 26 27 28 29 30 31 32 33, 34 35, 36 NC GND-clean GND-Reg Vdd VL CONFIG PWRDN TRI-STATE FAULT TH-WAR IN1A IN1B IN2A IN2B Vss VCCSIGN
Pin description Pin list (continued)
Name Not connected Logical ground Ground for regulator Vdd 5V Regulator referred to ground High logical state setting voltage Configuration Stand-by Hi-Z Fault pin advisor Thermal warning advisor Input of half bridge 1A Input of half bridge 1B Input of half bridge 2A Input of half bridge 2B 5-V regulator referred to +Vcc Signal positive supply Description
Table 3.
Pin FAULT (1) Logical value 0 1 0 TRI-STATE 1 0 PWRDN 1 THWAR (1) 0 1 0 CONFIG
(2)
Device status Fault detected (short circuit, or thermal) Normal operation All power stages in Hi-Z state Normal operation Low-power mode Normal operation Temperature of the IC =130 C Normal operation Normal Operation OUT1A = OUT1B, OUT2A = OUT2B (IF IN1A = IN1B and IN2A = IN2B)
1
1. The pin is open collector. To have the high logic value, it needs a pull-up resistor. 2. CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd).
3/11
Electrical specifications
STA510F
2
2.1
Electrical specifications
Absolute maximum ratings
Table 4.
Symbol VCC Vmax ESD Top Tstg, Tj
Absolute maximum ratings
Parameter DC supply voltage (Pin 4, 7, 12, 15) Maximum voltage on pins 23 to 32 Max ESD on pins (HBM) Operating temperature range Storage and junction temperature 44 5.5 1000 0 to 70 -40 to 150 Value Unit V V V C C
2.2
Thermal data
Table 5.
Symbol Tj-case TjSD Twarn thSD
Thermal data
Parameter Thermal resistance junction to case (thermal pad) Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis Min Typ 1 150 130 25 Max 2.5 Unit C/W C C C
2.3
Electrical specifications
Unless otherwise stated, the results in Table 6 below are given for the conditions: VL = 3.3 V, Vcc = 37 V and T = 25 C unless otherwise specified. Table 6.
Symbol RdsON Idss gN gP Dt_s Dt_d
Electrical specifications
Parameter Power Pchannel/Nchannel MOSFET RdsON Power Pchannel/Nchannel leakage current Power Pchannel RdsON matching Power Nchannel RdsON matching Low current dead time (static) High current dead time (dynamic) Id = 1 A Id = 1 A see test circuit Figure 3 L=22H, C = 470nF, RL = 8 , Id = 4.5 A, see test circuit Figure 4 95 95 10 20 50 Condition Id = 1 A Min Typ 150 Max 200 100 Unit m A % % ns ns
4/11
STA510F Table 6.
Symbol td ON td OFF tr tf VCC VIN-High
Electrical specifications Electrical specifications (continued)
Parameter Turn-on delay time Turn-off delay time Rise time Fall time Supply voltage operating voltage High level input voltage Condition Resistive load Resistive load Resistive load, as Figure 4 Resistive load, as Figure 4 10 VL/2 +300 mV Min Typ Max 100 100 25 25 40 Unit ns ns ns ns V V VL/2 300m V V Pin voltage = VL Pin voltage = 0.3V VL= 3.3V 1 1 35 A A A
VIN-Low IIN-H IIN-L IPWRDN-H
Low level input voltage High level input current Low level input current High level PWRDN pin input current Low logical state voltage (pins PWRDN, TRISTATE) (see Table 7) High logical state voltage (pins PWRDN, TRISTATE) (see Table 7)
VLow
VL = 3.3V
0.8
V
VHigh IVCCPWRDN
VL = 3.3V
1.7
V
Supply current from Vcc in power PWRDN = 0 down Output current pins FAULT -TH-WARN when FAULT CONDITIONS Supply current from Vcc in tristate Supply current from Vcc in operation both channel switching) Overcurrent protection threshold Isc (short circuit current limit) (note 2) Undervoltage protection threshold Output minimum pulse width No Load 25
3
mA
IFAULT
Vpin = 3.3V Pin TRI-STATE = 0 Input pulse width duty cycle = 50%, switching frequency = 384 kHz, no LC filters; 5.5
1 22
mA mA
IVCC-hiz
IVCC
70
mA
IOUT-SH
7
9
A
VUV tpw_min
7 40
V ns
5/11
Electrical specifications Table 7.
VL 2.7 3.3 5 0.7 0.8 0.85
STA510F
Vlow, Vhigh threshold variation with VL
VLow max 1.5 1.7 1.85 VHigh min V V V Unit
Table 8.
TRI-STATE 0 1 1 1 1
Logic truth table
INxA x 0 0 1 1 x 0 1 0 1 INxB Q1 OFF OFF OFF ON ON Q2 OFF OFF ON OFF ON Q3 OFF ON ON OFF OFF Q4 OFF ON OFF ON OFF Output mode Hi-Z DUMP NEGATIVE POSITIVE Not used
Figure 3.
Test circuit for low current dead time
OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50%
M58
DTr OUTxY
M57
DTf
INxY
R 8
+ -
V67 = vdc = Vcc/2
D03AU1458
gnd
Figure 4.
Test circuit for high current dead time
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC
Duty cycle=A
DTout(A) M58 Q1 OUTxA Rload=8 L67 22 C69 470nF DTout(B) L68 22 C70 470nF Q2 OUTxB M64
Duty cycle=B
DTin(A) INxA
DTin(B) INxB
Iout=4.5A M57 Q3
Iout=4.5A Q4 M63
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure
D00AU1162
6/11
STA510F Figure 5.
Electrical specifications Typical quad half-bridge configuration giving 200 W per channel into 4 speakers, 10% THD, VCC = 39 V
L201 OUT2B 15u C201 330p R201 20 C203 10n R203 20 C205 1u C207 330n R202 20 C202 330p L202 C8 R204 20 C204 10n 15u OUT2A 100n IN 2B IN 2A IN 1B IN 1A C7 100n C206 1u 4 ohm
STA510F
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VccSig VccSig Vss Vss IN2B IN2A IN1B IN1A TH_WARN FAULT TRISTATE PWRDN CONFIG Ibias Vdd Vdd GNDReg GNDClean GND Sub OUT2B OUT2B Vcc2B GND2B GND2A Vcc2A OUT2A OUT2A OUT1B OUT1B Vcc1B GND1B GND1A Vcc1A OUT1A OUT1A NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Vcc + C2 C3 1u C4 100n 100n C1 1000u
PWM Input
TH_W EAPD
R2 10K 3V3
R1 10k C11 100n
3V3
C9 100n C10 100n
OUT1B L101 15u C101 330p R101 20
C5 1u
C6 100n
C103 10n R103 20 C105 1u C107 330n
R102 20 C102 330p OUT1A L102 15u
R104 20 C104 10n
C106 1u
4 ohm
Figure 6.
Typical driving configuration with STA330
7/11
Package information
STA510F
3
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: http://www.st.com. Figure 7. PowerSO36 package dimensions
DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s MIN. 3.25 3.1 0.8 0.030 0.22 0.23 15.8 9.4 1 13.9 10.9 5.8 2.9 0.65 11.05 0 15.5 0.8 0.075 15.9 1.1 1.1 10 8 0 0.61 0.031 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.228 0.114 0.026 0.435 0.003 0.625 0.043 0.043 10 8 mm TYP. MAX. 3.43 3.2 1 -0.040 0.38 0.32 16 9.8 MIN. 0.128 0.122 0.031 0.0011 0.008 0.009 0.622 0.37 0.039 0.57 0.437 0.114 0.244 1.259 inch TYP. MAX. 0.135 0.126 0.039 -0.0015 0.015 0.012 0.630 0.38
OUTLINE AND Outline and mechanical data MECHANICAL DATA
0.2
0.008
(1) "D and E1" do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006") (2) No intrusion allowed inwards the leads.
PowerSO36 (SLUGup) (exposed pad (slug) UP)
PowerS036
7183931 D
8/11
STA510F
Trademarks and other acknowledgements
4
Trademarks and other acknowledgements
FFX is a STMicroelectronics proprietary digital modulation technology. DDX is a registered trademark of Apogee Technology, Inc. ECOPACK is a registered trademark of STMicroelectronics.
9/11
Revision history
STA510F
5
Revision history
Table 9.
Date 13-Dec-2007
Document revision history
Revision 1 Initial release. Changes
10/11
STA510F
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